A multiprocessor system requires a manner of granting, to one process/processor pair at a time, exclusive access to protected resources during selected operations which must not be interrupted, called atomic operations. Upon this primitive notion, much more elaborate interprocess control and communication mechanisms can be built. Most typically, the protected resources will be memory data structures such as process control blocks or synchronization semaphores or queues.
The most common approach to supporting such a facility in a computer instruction set is to define one or more instructions to have two indivisible actions of which one is conditioned upon the other. The TEST.sub.-- AND.sub.-- SET instruction and the COMPARE.sub.-- AND.sub.-- SWAP instructions of the Motorola 68020 instruction set typify this type of approach. These are actions so very primitive that another layer of more capable primitives must immediately be added, such as list entry ENQUEUE or process NOTIFY. In the context of a Reduced Instruction Set Computer (RISC) processor architecture, there is yet another important disadvantage, wherein this type of primitive will typically be multicycle and rather elaborate to implement.